Upon doing so, you should see the available libraries listed in the Workspace. These and a few others should already be setup for ModelSim XE III. OkFPsim_v2_ver = C:/Program Files/Opal Kelly/FrontPanel/FrontPanelHDL/ModelSimXE6_v2/okFPsim_v2_verįor many projects, you will need to have the Unisim and Xilinx Corelib libraries linked as well.

Xilinxcorelib_ver = $MODEL_TECH/./xilinx/verilog/xilinxcorelib_verĪim_ver = $MODEL_TECH/./xilinx/verilog/aim_verĬpld_ver = $MODEL_TECH/./xilinx/verilog/cpld_ver

Simprims_ver = $MODEL_TECH/./xilinx/verilog/simprims_ver Unisims_ver = $MODEL_TECH/./xilinx/verilog/unisims_ver OkFPsim_v2 = C:/Program Files/Opal Kelly/FrontPanel/FrontPanelHDL/ModelSimXE6_v2/okFPsim_v2 Xilinxcorelib = $MODEL_TECH/./xilinx/vhdl/xilinxcorelib Simprim = $MODEL_TECH/./xilinx/vhdl/simprim Unisim = $MODEL_TECH/./xilinx/vhdl/unisim It should now look a lot like the text below: VHDL Section Edit the section near the top of the file that defines the library locations to add the FrontPanel Library links. This can be done several ways, but only one will be described here.įind the modelsim.ini file in your ModelSim installation directory. Next, ModelSim must find the FrontPanel simulation libraries. The following files from DESTutorial.zip (Part4) are required: Once you have a version of ModelSim 6 installed on your machine, we need to make sure your main DES project directory is setup properly. Please visit their website for an updated distribution if you’re interested in using that core. Note: The DES core that is integral to this part of the tutorial was written by Rudolf Usselmann and provided to. They were compiled under the free ModelSim XE III Starter 6.0a and typically be refreshed for usage under newer versions of ModelSim SE and PE. The FrontPanel simulation libraries are currently distributed in Verilog and VHDL libraries. These libraries make it possible to call functions from an HDL test fixture that mimic the operation of FrontPanel API calls. Instead, all FrontPanel HDL components are replaced by modules in the FrontPanel simulation libraries. We are also assuming that the user is working with the Verilog sample of the DES Tester for XEM3001v2.įor simulation, the okLibrary.v or okLibrary.vhd files are not required. In this part of the tutorial, the PC/FPGA connectivity shown in Part III will be performed in simulation by the free ModelSim XE III (available from Xilinx). Part IV – ModelSim Behavioral Simulation of FrontPanel APIĪpproximate time to complete this part: 45 minutes Please review the FrontPanel User’s Manual for the latest information and use the current Samples (and their README) from your installation as guidance. Note: This tutorial is outdated and no longer maintained to be consistent with the latest FrontPanel SDK or Xilinx tools.

Modelsim tutorial verilog